Synopsys today announced the successful tape-out of a broad portfolio of DesignWare Interface and Foundation IP on TSMC's 10-nanometer (nm) FinFET process, reducing risk for designers who want to take advantage of the power, area and performance improvements offered by the process.
Achieving this tape-out milestone enables designers to accelerate the development of SoCs that incorporate USB 3.1, USB 3.0, USB 2.0, HSIC, PCI Express 3.0, PCI Express 2.0 and MIPI D-PHY interface IP.
In addition, Synopsys is developing embedded memories, DDR4, LPDDR4 and MIPI M-PHY IP, which will further extend its 10-nm IP portfolio. TSMC's 10-nm process provides 2.2 times the logic density, a 15 percent performance improvement, and 35 percent power reduction compared to their 16-nm FinFET Plus process node.
Taking advantage of the process, Synopsys has re-architected its IP at 10 nm for lower power, higher performance and smaller area compared to the previous generation. As an example, the high-speed SerDes-based PHYs consume less than 5mW/Gb/lane.
"As the leading provider of physical IP, Synopsys has collaborated with TSMC on the development of IP for the 10-nanometer process, enabling designers to achieve the design goals of their next-generation SoCs," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "By offering a broad portfolio of IP at the TSMC 10-nanometer node, Synopsys is reducing the risks associated with moving to this new process technology."
"Synopsys' track record of providing high-quality IP through many generations of TSMC processes, including 10 nanometers, offers designers a low-risk path to integrating high-performance IP into their SoCs," said Suk Lee, TSMC senior director, design infrastructure marketing division.
"Our close collaboration with Synopsys on the development of IP for the TSMC 10-nanometer process enables our mutual customers to reduce their power and area, increase performance and accelerate their time to volume production."
