HSINCHU, Taiwan - Macronix International today announces that it has four technical papers selected for presentation at 2017 IEEE International Electron Devices Meeting (IEDM) which is taking place in San Francisco, USA from December 2-6. One of these four papers that describes a novel 3D NAND structure, called single-gate vertical channel (SGVC), was further chosen as a Highlight Paper, the only one from Taiwan.
The Highlight Paper selected for 2017 IEDM focuses on realizing a 128Gb MLC (or 192Gb TLC) 3D NAND Flash using the SGVC architecture with only 16 layers. Such memory density is comparable to 48-layer 3D NAND using a popular gate-all-around (GAA) structure. SGVC has the important advantage of much smaller cell size and pitch scaling capability which allows very high-density memory with much fewer stacking layers.
The 3D SGVC NAND makes use of arrays of vertically arranged single-gate flat-cell thin film transistors with an ultra-thin body, which aren’t as sensitive to variation of critical dimensions (CD) as GAA devices, and is very suitable for read-intensive memory applications.
The other three Macronix papers chosen for 2017 IEDM include one that proposes a model to understand the operational physics of junction-free structure and Wordline (WL) interference effects in a 3D NAND. Another paper deals with ovonic threshold switching (OTS) chalcogenide material system (TeAsGeSi) that incorporates Se and an extra dopant. The resulting new selector demonstrated excellent endurance and OTS characteristics suitable for 3D stackable cross-point high-density non-volatile memory. The third one discusses retention behavior of high resistance state (HRS) of ReRAMs (resistive random access memories).
Macronix has published more than 60 papers at IEDM since 2003. In 2012 Macronix presented two Highlight Papers. This year, there are 16 Highlight Papers for IEDM, Macronix’s paper is the only one from Taiwan-based companies and academic institutes.
