Synopsys announced the demonstration of MIPI D-PHY IP on TSMC's 16-nanometer (nm) FinFET Plus (16FF+) process operating at 2.5 Gbps per lane. The demonstration shows the DesignWare D-PHY receiver (Rx) lane connected to Keysight Technologies' test equipment, which provided burst-mode stimulus for stressed eye testing and the transmitter (Tx) lane connected to the Keysight oscilloscope displaying the transmitter's performance.
The DesignWare MIPI D-PHY operating at very high speeds on the 16FF+ process, enables designers to meet their power and performance requirements while ensuring interoperability with the latest image sensors and displays. Synopsys' silicon-proven D-PHY IP is compliant with the MIPI D-PHY v1.2 specification and delivers 50 percent lower power and smaller area compared to other competitive solutions.
"Keysight and Synopsys collaborated to validate the performance and compliance of the DesignWare MIPI D-PHY IP, helping designers lower the risk of incorporating the IP into their SoCs," said Jurgen Beck, vice president and general manager at Keysight Technologies. "This industry first demonstration underscores both companies' commitment to providing designers with high-quality IP and testing solutions that enable them to meet their design requirements and achieve silicon success."
"Synopsys' demonstration gives designers assurance that they can incorporate DesignWare MIPI D-PHY IP into their SoC with confidence, while meeting their power and performance goals on the advanced 16FF+ process," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "Synopsys' MIPI IP solutions have been used in hundreds of designs. This successful track record combined with the demonstration enables designers to incorporate a high-quality D-PHY solution into their SoCs with minimal risk."
