Keysight Technologies today expanded its M8000 Series bit error ratio test solutions with a 32-Gb/s BERT front end and integrated capabilities for higher-data-rate testing. The newly integrated capabilities streamline testing for R&D and test engineers who need to characterize devices and systems for next-generation data-center and long-haul-communication applications.
The M8062A 32-Gb/s module expands the J-BERT M8020A high-performance BERT with versatile generator and analyzer functionality at data rates up to 32.4 Gb/s.
In the past, engineers had to integrate separate instruments to create a solution for characterizing multichannel 32-Gb/s devices and systems, which impacted measurement repeatability and test setup and reconfiguration time. J BERT's fully integrated capabilities, such as inter symbol interference (ISI) generation, clock data recovery and analyzer equalization greatly improve device characterization and compliance testing and significantly simplifies test setups.
At higher data rates, such as 100G, more complex methods are used to mitigate the effects of higher channel loss. Receiver equalization consisting of CTLE (continuous time linear equalization) and possibly DFE (decision feedback equalization) increase the complexity of receiver designs. Verifying these designs requires testing with a variety of channel losses. The integrated ISI generation allows engineers to test receivers over a range of channel losses without the need to manually reconfigure cables on external ISI channel boards, which improves measurement reliability and repeatability and saves time.
The analyzer equalization functionality improves measurement accuracy and repeatability at higher data rates by "opening closed eyes" in the looped-back signal from the device under test (DUT) to the BERT error analyzer. To measure a bit error ratio correctly, the sampler within the error analyzer requires a sufficiently open eye. High input sensitivity in the error analyzer isn't sufficient to overcome closed eyes at high date rates, where there is more eye closure. At higher data rates, these signals can suffer the same degradation as the signal in the test channel. Without proper equalization, bit error ratio measurements can be confounded by adding errors in the error analyzer itself as opposed to the true errors from the DUT.
"This expansion of our M8000 Series bit error ratio testers to 32 Gb/s embodies our M8000 test philosophy of higher integration and best accuracy and makes it ideal for high-speed data-center applications," said Jurgen Beck, vice president and general manager of Keysight's Digital and Photonic Test Division. "BER test setups often need to be reconfigured several times during a single test session. With these functions integrated within the BERT itself, engineers can modify test settings without the need to reconfigure test setup or cabling."
Engineers can control the emulated channel loss, integrated CDR and analyzer equalizer function through the integrated user interface in M8070A system software for M8000 BER test solutions or through remote programming commands to allow test automation.
